CD74AC164M96

Texas Instruments
595-CD74AC164M96
CD74AC164M96

Mfr.:

Description:
Counter Shift Registers 8-Bit Ser-In/Prl-Out Shift Register A 59 A 595-CD74AC164M

ECAD Model:
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In Stock: 2,316

Stock:
2,316 Can Dispatch Immediately
Factory Lead Time:
6 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 2500)

Pricing (USD)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
$0.69 $0.69
$0.493 $4.93
$0.442 $11.05
$0.386 $38.60
$0.359 $89.75
$0.343 $171.50
$0.33 $330.00
Full Reel (Order in multiples of 2500)
$0.313 $782.50
$0.301 $2,257.50
† A MouseReel™ fee of $7.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Alternative Packaging

Mfr. Part No.:
Packaging:
Tube
Availability:
In Stock
Price:
$1.14
Min:
1

Similar Product

Texas Instruments CD74AC164M
Texas Instruments
Counter Shift Registers 8-Bit Ser-In/Prl-Out Shift Register
End of Life: Scheduled for obsolescence and will be discontinued by the manufacturer.

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Counter Shift Registers
RoHS:  
Serial to Parallel
1 Circuit
8 bit
SOIC-14
74AC
CMOS
2
157 ns, 17.5 ns, 12.5 ns
1.5 V
5.5 V
- 55 C
+ 125 C
Reel
Cut Tape
MouseReel
Brand: Texas Instruments
Function: Shift Register
Mounting Style: SMD/SMT
Number of Output Lines: 8
Operating Supply Voltage: 1.5 V to 5.5 V
Product Type: Counter Shift Registers
Series: CD74AC164
Factory Pack Quantity: 2500
Subcategory: Logic ICs
Unit Weight: 129.400 mg
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CNHTS:
8542399000
CAHTS:
8542310000
USHTS:
8542390090
KRHTS:
8542311000
TARIC:
8542319000
MXHTS:
8542310399
ECCN:
EAR99

CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers

Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.