CDCUA877NMKR

CDCUA877 Phase-Lock Loop Clock Driver

Texas Instruments CDCUA877 Phase-Lock Loop Clock Driver is a high-performance, low-jitter, low-skew, zero-delay buffer. It distributes a differential clock input pair (CK, /CK) to 10 differential pairs of clock outputs (Yn, /Yn) and one differential pair of feedback clock outputs (FBOUT, /FBOUT). The clock outputs are controlled by the input clocks (CK, /CK), the feedback clocks (FBIN, /FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the clock outputs, except FBOUT, /FBOUT, are disabled while the internal PLL maintains its locked-in frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions as previously described. When OS and OE are both low, OE does not affect Y7, /Y7, as these are free-running. When AV_DD is grounded, the PLL is turned off and bypassed for test purposes.