LMX1205RHAT

Texas Instruments
595-LMX1205RHAT
LMX1205RHAT

Mfr.:

Description:
Phase Locked Loops - PLL Low-noise high-freq uency buffer/multipl

Lifecycle:
New Product:
New from this manufacturer.
ECAD Model:
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In Stock: 144

Stock:
144 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:
This Product Ships FREE

Pricing (USD)

Qty. Unit Price
Ext. Price
$292.05 $292.05
$251.01 $2,510.10
$240.76 $6,019.00
Full Reel (Order in multiples of 250)
$224.05 $56,012.50

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Phase Locked Loops - PLL
RoHS:  
12.8 GHz
300 MHz
300 MHz to 12.8 GHz
2.6 V
2.4 V
Si
- 40 C
+ 85 C
SMD/SMT
VQFN-40
Reel
Cut Tape
Brand: Texas Instruments
Development Kit: LMX1205EVM
Input Level: CMOS
Moisture Sensitive: Yes
Operating Supply Current: 1.13 A
Operating Supply Voltage: 2.5 V
Product Type: PLLs - Phase Locked Loops
Series: LMX1205
Factory Pack Quantity: 250
Subcategory: Wireless & RF Integrated Circuits
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Attributes selected: 0

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CNHTS:
8542399000
USHTS:
8542390090
TARIC:
8542399000
MXHTS:
8542399999
ECCN:
EAR99

LMX1205 JESD Buffer/Multiplier/Divider

Texas Instruments LMX1205 JESD Buffer/Multiplier/Divider has a high-frequency capability, extremely low jitter, and programmable clock input and output delay. These features make this device a great approach to clock high precision, high-frequency data converters without degradation of signal-to-noise ratio. Each of the four high-frequency clock outputs and additional LOGICLK outputs with a larger divider range is paired with a SYSREF output clock signal. The SYSREF signal for JESD204B/C interfaces can either be passed or internally generated as input and re-clocked to the device clocks. The noiseless delay adjustment at the input path of the high-frequency clock input and individual clock output paths ensures low-skew clocks in a multi-channel system. For the data converter clocking application, having the jitter of the clock less than the aperture jitter of the data converter is essential. In applications where more than four data converters need to be clocked, various cascading architectures can be developed using multiple devices to distribute all the SYSREF signals and high-frequency clocks required. The Texas Instruments LMX1205 is an exemplary choice for clocking data converters when combined with an ultra-low noise reference clock source, especially when sampling above 3GHz.