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RoHS

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AS4C128M32MD4-062BAN

Name: Alliance Memory AS4C128M32MD4-062BAN
Brand: Alliance Memory
SKU: 913-C128M32MD4062BAN
Price: 45.99 USD
Availability: OutOfStock

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Mouser No:

913-C128M32MD4062BAN

Mfr. No:

AS4C128M32MD4-062BAN

Mfr.:

Alliance Memory

Description:

DRAM LPDDR4, 4G, 128M x 32, 1.1V, 200 BALL TFBGA, 1600MHZ, ECC, AUTO TEMP - Tray

Datasheet:

AS4C128M32MD4-062BAN Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C128M32MD4-062BAN

Availability

Stock:: 0

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On Order:: 679

Expected 2026/07/06
Factory Lead Time:: 20

Weeks Estimated factory production time for quantities greater than shown.

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Minimum: 1 Multiples: 1

Unit Price:

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Ext. Price:

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Est. Tariff:

Pricing (USD)

Qty.	Unit Price	Ext. Price
	$45.99	$45.99
	$42.54	$425.40
	$41.18	$1,029.50
	$40.18	$2,009.00
	$39.05	$3,905.00
	$38.70	$10,526.40
2,584	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM Mobile - LPDDR4
Memory Size:	4 Gbit
Data Bus Width:	32 bit
Maximum Clock Frequency:	1.6 GHz
Package/Case:	FBGA-200
Organisation:	128 M x 32
Access Time:	3.5 ns
Supply Voltage - Min:	1.06 V
Supply Voltage - Max:	1.95 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 105 C
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	136
Subcategory:	Memory & Data Storage
Supply Current - Max:	79 mA

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Datasheet

AS4C128M32MD4-062BAN Datasheet (PDF)

REACH Declaration (PDF)

USHTS:: 8542320036
ECCN:: EAR99

2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM

Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM is organized as 1 or 2 channels per device, and the individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is a 16n prefetch architecture with an interface. It's designed to transfer two data words per clock cycle at the I/O pins. These devices offer fully synchronous operations referenced to the rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.