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RoHS

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AS4C512M32MD4V-046BIN

Name: Alliance Memory AS4C512M32MD4V-046BIN
Brand: Alliance Memory
SKU: 913-AS4C512M32MD4V46
Price: 89.12 USD
Availability: InStock

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Mouser No:

913-AS4C512M32MD4V46

Mfr. No:

AS4C512M32MD4V-046BIN

Mfr.:

Alliance Memory

Description:

DRAM LPDDR4X, 16Gb, 512M x 32, 0.6V, 200ball TFBGA, 2133MHZ, INDUSTRIAL TEMP

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

AS4C512M32MD4V-046BIN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C512M32MD4V-046BIN

In Stock: 455

Stock:: 455 Can Dispatch Immediately

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Factory Lead Time:: 30 Weeks Estimated factory production time for quantities greater than shown.

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Unit Price:

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Ext. Price:

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$89.12	$89.12
	$82.19	$821.90
	$79.50	$1,987.50
	$77.50	$3,875.00
	$77.48	$9,297.60
240	Quote

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - LPDDR4X
Memory Size:	16 Gbit
Data Bus Width:	32 bit
Maximum Clock Frequency:	2.133 GHz
Package/Case:	FBGA-200
Organisation:	512 M x 32
Access Time:	3.5 ns
Supply Voltage - Min:	1.7 V
Supply Voltage - Max:	1.95 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 95 C
Series:	AS4C
Packaging:	Tray
Brand:	Alliance Memory
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	KR
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	120
Subcategory:	Memory & Data Storage
Supply Current - Max:	10 mA

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Datasheet

AS4C512M32MD4V-046BIN Datasheet (PDF)

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CNHTS:: 8542329010
CAHTS:: 8542320020
USHTS:: 8542320036
MXHTS:: 8542320299
ECCN:: EAR99

2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM

Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM is organized as 1 or 2 channels per device, and the individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is a 16n prefetch architecture with an interface. It's designed to transfer two data words per clock cycle at the I/O pins. These devices offer fully synchronous operations referenced to the rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.