SN74SSTU32864NMJR

Texas Instruments
595-N74SSTU32864NMJR
SN74SSTU32864NMJR

Mfr.:

Description:
Clock Buffer 500-MHz 25-bit conf igurable registered

ECAD Model:
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In Stock: 945

Stock:
945 Can Dispatch Immediately
Factory Lead Time:
12 Weeks Estimated factory production time for quantities greater than shown.
Quantities greater than 945 will be subject to minimum order requirements.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 1000)

Pricing (USD)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
$19.58 $19.58
$15.64 $156.40
$14.65 $366.25
$13.57 $1,357.00
$13.05 $3,262.50
$12.75 $6,375.00
Full Reel (Order in multiples of 1000)
$12.40 $12,400.00
2,000 Quote
† A MouseReel™ fee of $7.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Clock Buffer
RoHS:  
25 Output
500 MHz
2.7 ns
SSTL-18
NFBGA-96
SSTL-18
500 MHz
1.7 V
1.9 V
SN74SSTU32864
0 C
+ 70 C
Brand: Texas Instruments
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Packaging: Reel
Packaging: Cut Tape
Packaging: MouseReel
Product: Clock Buffers
Product Type: Clock Buffers
Factory Pack Quantity: 1000
Subcategory: Clock & Timer ICs
Type: 25-Bit Configurable Registered Buffer
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USHTS:
8542390090
ECCN:
EAR99

SN74SSTU32864 Configurable Registered Buffer

Texas Instruments SN74SSTU32864 25-Bit Configurable Registered Buffer is a 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the LVCMOS reset (RESET)\ and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The Texas Instruments SN74SSTU32864 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.