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EVLSTGAP3SXS-H

Name: STMicroelectronics EVLSTGAP3SXS-H
Brand: STMicroelectronics
SKU: 511-EVLSTGAP3SXS-H
Price: 58.51 USD
Availability: InStock

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Mouser No:

511-EVLSTGAP3SXS-H

Mfr. No:

EVLSTGAP3SXS-H

Mfr.:

STMicroelectronics

Description:

Power Management IC Development Tools Half-bridge evaluation board for STGAP3SXS SiC MOSFETs isolated gate driver with

Complete Your Design

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

EVLSTGAP3SXS-H Datasheet (PDF)

More Information

Learn more about STMicroelectronics EVLSTGAP3SXS-H

In Stock: 40

Stock:: 40

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On Order:: 28

Expected 2027/02/19
Factory Lead Time:: 52

Weeks Estimated factory production time for quantities greater than shown.

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Minimum: 1 Multiples: 1 Maximum: 10

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Pricing (USD)

Qty.	Unit Price	Ext. Price
	$58.51	$58.51

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	STMicroelectronics
Product Category:	Power Management IC Development Tools
RoHS:
Product:	Evaluation Boards
Type:	Gate Driver
Input Voltage:	5 V
Tool Is For Evaluation Of:	STGAP3SXS
Series:	STGAP3SXS
Brand:	STMicroelectronics
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	IT
Packaging:	Bulk
Product Type:	Power Management IC Development Tools
Factory Pack Quantity:	1
Subcategory:	Development Tools
Unit Weight:	150 g

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Datasheet

EVLSTGAP3SXS-H Datasheet (PDF)

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CAHTS:: 9030820000
USHTS:: 9030820000
KRHTS:: 9030820000
TARIC:: 9030820000
MXHTS:: 9030820100
ECCN:: EAR99

EVLSTGAP3SXS-H Half-Bridge Evaluation Board

STMicroelectronics EVLSTGAP3SXS-H Half-Bridge Evaluation Board is designed to evaluate the STGAP3SXS isolated single-gate driver. The STGAP3SXS is characterized by 10A current capability, rail-to-rail outputs, and optimized UVLO and DESAT protection thresholds for SiC MOSFETs. This feature makes the device optimal for high-power motor drivers in industrial applications. The gate driver has a single output pin and a driver line for an external Miller CLAMP N-channel MOSFET. This option optimizes positive and negative gate spike suppression during fast commutations in half-bridge topologies.