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Texas Instruments SN74AUP1T02 Single 2-Input Positive-NOR Gates

Texas Instruments SN74AUP1T02 Single 2-Input Positive-NOR Gates perform the Boolean function Y = A\ + B\ or Y = A\ • B\ with designation for logic-level translation applications with output referenced to supply VCC. AUP technology is low-power logic technology designed to extend battery life while operating. All input levels accept 1.8V LVCMOS signals while operating from either a single 3.3V or 2.5V VCC supply. This product also maintains excellent signal integrity.

The wide VCC range of 2.3V to 3.6V allows the possibility of switching output levels to connect to external controllers or processors. Schmitt-trigger inputs (VT = 210mV between negative and positive input transitions) improve noise immunity during switching transitions, especially useful on analog mixed-mode designs. Schmitt-trigger inputs ensure the integrity of output signals, reject input noise and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0V) and is important in portable and mobile applications. When VCC = 0V, signals ranging from 0V to 3.6V can be applied to the device's inputs and outputs. No damage occurs to the device under these conditions. The Texas Instruments SN74AUP1T02 is designed with an optimized current-drive capability of 4mA to reduce line reflections, undershoot, and overshoot caused by high-drive outputs. This device is ideal for logic-level translation applications.

Features

  • Single-supply voltage translator
  • Output level up to supply VCC CMOS level
    • 1.8V to 3.3V (at VCC = 3.3V)
    • 2.5V to 3.3V (at VCC = 3.3V)
    • 1.8V to 2.5V (at VCC = 2.5V)
    • 3.3V to 2.5V (at VCC = 2.5V)
  • Schmitt-trigger inputs reject input noise and provide better output signal integrity
  • Ioff supports partial power down (VCC = 0V)
  • Very low static power consumption of 0.1µA
  • Very low dynamic power consumption of 0.9µA
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Pb-free package is available (SC-70 (DCK))
  • 2mm x 2.1mm x 0.65mm (height 1.1mm)
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)

Resource

Logic Diagram (NOR Gate)

Block Diagram - Texas Instruments SN74AUP1T02 Single 2-Input Positive-NOR Gates

Development Tool

Texas Instruments 5-8-LOGIC-EVM Evaluation Module

Developed to support leaded Logic devices in the DBV, DCK, DCT, DCU, and DRL packages.

Learn Moreabout Texas Instruments 5-8-LOGIC-EVM Evaluation Module View Productsrelated to Texas Instruments 5-8-LOGIC-EVM Evaluation Module
Published: 2025-02-19 | Updated: 2025-02-24